This invention relates, in general, to semiconductor devices and, more particularly, to a means and method for providing an insulating isolaion wall for electrically isolating one portion of an integrated semiconductor device structure or circuit from another. The isolation wall is formed in a trench provided in the semiconductor substrate.
The copending application by Robert Mattox et al., U.S. Ser. No. 122,086, entitled "Trench Isolation Process and Structure", and the copending application of Bridgette A. Bergami, et al, U.S. Ser. No. 122,091, entitled "Multilayer Trench Isolation Process and Structure", are related.
It is commonplace to provide isolation walls between adjacent devices or device regions in integrated circuits, particularly bipolar integrated circuits. In the prior art these isolation walls have been formed of a dielectric such as silicon dioxide or a combination of silicon dioxide and polycrystalline silicon. A disavantage of using thermally grown silicon dioxide for the isolation walls is that oxide growth progresses laterally as well as vertically making achievement of small lateral dimensions and precise dimensional control more difficult. In addition, trapped voids are frequently formed when oxide is used, particularly in trenches whose depth is equal to or larger than their width. Trapped voids are undesirable.
Further, silicon dioxide, which is the most commonly used trench refill material, whether grown or deposited, has a different coefficient of thermal expansion than most semiconductor substrates. As a consequence, when the semiconductor wafer is heated and cooled during processing, the differential thermal expansion and contraction of the isolation wall of the substrate can induce great stress in the semiconductor substrate. This leads to defect formation in the substrate adjacent the isolation wall, which is undesirable.
It is known in the prior art to replace part of the dielectric of the isolation wall with a polycrystalline semiconductor of the same material as the substrate. The poly region is isolated from the substrate by a thin oxide region on the sides of the isolation wall trench or is doped so as to form a PN junction with the single crystal semiconductor substrate material, or both. While the use of such a polycrystalline plug in the isolation wall can reduce the differential expansion mismatch, it creates other problems well known in the art.
In a related application by Robert Mattox et al., noted above, a means and method for overcoming a number of the limitations of the prior art are described in which an oxy-nitride is used as the principal material for filling the isolation trenches. In this process trenches are etched in the semiconductor substrate and filled with a low stress oxy-nitride. The oxy-nitride is then planarized with, for example a photoresist, and etched back to the semiconductor surface. However, this process and structure suffer from the limitation that there is no etch-stop provided to protect the substrate surface during planarization etching of the trench material or permit easy adjustment of the height of the trench filling material relative to the substrate surface. Accordingly, the oxy-nitride in the trenches may be over etched and severely recessed and the substrate surface may be damaged.
Accordingly, it is an object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits.
It is an additional object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits formed by etch-out and refill, wherein an etch-stop layer is provided to allow improved control of the etch-back and planarization process.
It is a further object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits wherein the coefficient of thermal expansion of the wall material is advantageously controlled relative to the semiconductor substrate, and in which any latent voids or etch sensitive regions of the as-deposited wall material are removed and replaced by an etch resistant dielectric.
It is an additional object of the present invention to provide an etch-stop to facilitate planarization of the wall material while minimizing substrate surface damage.